N-channel MOSFETs are made up of an
N-type source and drain that are diffused on a P-type substrate.
Electrons make up the vast majority of carriers. The NMOS will conduct
when the gate voltage is sufficiently high; otherwise, it will not. NMOS
is considered to be faster than PMOS since the majority of carriers
(electrons) travel faster than holes.
A Source and Drain are also diffused on a substrate in P-channel MOSFETs. The source is of the P type, while the substrate is of the N type. The vast majority of carriers are voids. When a low voltage is provided, PMOS will conduct. The PMOS will not conduct if a high voltage is applied to the gate.
As CMOS technology employs both N-type and P-type transistors in the creation of logic functions, a signal that turns on one transistor type is utilized to turn off the other. This replaces the need for pull-up resistors with simple switches. N-type MOSFETs are organized in a pull-down network between the output and the low voltage supply rail (VSS or ground) in CMOS logic gates, whereas P-type MOSFETs are positioned in a pull-up network between the output and the higher-voltage rail (typically VDD). As a result, when the P-type MOSFET is turned off, the N-type MOSFET is turned on, and vice versa. For any given input pattern, one of the networks is turned on and the other is turned off. High speed, low power dissipation, high noise margins in both states, and a wide range of source and input voltages (fixed source voltage) are all advantages of CMOS.
CMOS (CMOS Logic Gates)
1) Inverter CMOS
The most basic CMOS logic gate is the inverter. The circuit is made up of PMOS and NMOS FETs. The gate voltage for both transistors is provided by input A, while the output is provided by Y.
The NMOS transistor is powered by VSS or ground, while the PMOS transistor is powered by VDD. When the input (A) is low (VDD, 0 V, Logic 0), the NMOS is turned off and the PMOS is turned on. VDD will be seen at the output via the P-channel MOSFET circuit. As a result, with the circuit pushed up to VDD, there is output (Logic 1). When the input is high (VDD, Logic 1), the PMOS is turned off and the NMOS is turned on. The output has been brought down and is hence low (Logic 0).
2) CMOS NAND Gate
Two N-channel MOSFETs are connected in series between Y (output) and
GND in a 2-input NAND gate, and two P-channel MOSFETs are connected in
parallel between VDD and Y
At least one of the NMOS transistors will be turned off if either A or B is low (Logic 0). Because the NMOS transistors are coupled in series, this interrupts the flow from Y to GND. In this situation, however, at least one of the PMOS transistors is turned on, completing the circuit from Y to VDD. This raises the output Y (Logic 1). For Y to be low, both A and B must be high in order for both NMOS transistors to be ON and the path from Y to GND to be complete. Y will be positive for all other input combinations. The NAND logic gate truth table is shown below.
3) CMOS NOR Gate
The NMOS transistors of a 2-input NOR gate are connected in parallel, whereas the PMOS transistors are connected in series. At least one NMOS transistor pulls the output low when at least one of the inputs is high. Only when both inputs are low is the output high.
The NOR logic gate truth table is shown below.
Because of its efficiency in using electric power and adaptability, CMOS is the dominating technique for IC production. The low-power design produces less heat and is the most dependable of the present technologies. Depending on the circuit design, P-type and N-type transistors can be arranged to produce logic gates.